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april 2009 ? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 fin1049 ? lvds dual-line driver with dual-line receiver fin1049 lvds dual-line driver with dual-line receiver features ? greater than 400mbps data rate ? 3.3v power supply operation ? low power dissipation ? fail-safe protection for open-circuit conditions ? meets or exceeds tia/eia-644-a lvds standard ? 16-pin tssop package saves space ? flow-through pinout simplifies pcb layout ? enable/disable for all outputs ? industrial operating temperature range: -40c to +85c description this dual driver-receiver is designed for high-speed interconnects utilizing low voltage differential signaling (lvds) technology. the driver accepts lvttl inputs and translates them to lvds outputs. the receiver accepts lvds inputs and translates them to lvttl outputs. the lvds levels have a typical differential output swing of 350mv, which provides for low emi at ultra-low power dissipation even at high frequencies. the fin1049 can accept lvpecl inputs for translating from lvpecl to lvds. the en and enb inputs are anded together to enable/disable the outputs. the enables are common to all four outputs. a single-line driver and single-line receiver function is also available in the fin1019. ordering information part number operating temperature range eco status package packing method FIN1049MTCX -40 to +85c rohs 16-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide tape and reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 2 fin1049 ? lvds dual-line driver with dual-line receiver pin configuration functional diagram figure 1. pin configuration figure 2. functional diagram pin definitions pin # name description 2, 3 r in1+ , r in2+ non-inverting lvds inputs 1, 4 r in1- , r in2- inverting lvds inputs 7, 6 d out1+ , d out2+ non-inverting driver outputs 8, 5 d out1- , d out2- inverting driver outputs 16, 9 en, enb driver enable pins for all outputs 15, 14 r out1 , r out2 lvttl output pins for r out1 and r out2 10, 11 d in1 , d in2 lvttl input pins for d in1 and d in2 12 v cc power supply (3.3v) 13 gnd ground function table inputs outputs (lvttl) inputs (lvds) (1) outputs (lvds) en enb r out1 r out2 r inn+ r inn- d outn+ d outn- h l on on on on h h z z z z l h z z z z l l z z z z h l h h open current fail-safe condition legend: h=high logic level l=low logic level or open x=don't care z=high impedance note: 1. any unused receiver inputs should be left open.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 3 fin1049 ? lvds dual-line driver with dual-line receiver absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 +4.6 v v in lvds dc input voltage -0.5 +4.6 v v out lvds dc output voltage -0.5 +4.6 v i osd driver short-circuit current (continuous) 10 ma t stg storage temperature range -65 +150 c t j max junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c human body model, jesd22-a114 7000 esd machine model, jesd22-a115 250 v recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v |v id | magnitude of differential voltage 100 v cc mv t a operating temperature -40 +85 c
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 4 fin1049 ? lvds dual-line driver with dual-line receiver dc electrical characteristics over-supply voltage and operating temperature ranges, unless ot herwise specified. all typical values are at t a =25c and with v cc =3.3v. symbol parameter conditions min. typ. max. units lvds input dc specifications (r in1+ , r in1- , r in2+ , r in2- ) see figure 3 and table 1 v th differential input threshold high v cm =1.2v, 0.05v, 2.35v 0 35 mv v tl differential input threshold low -100 0 mv v ic common mode voltage range v id =100mv, v cc =3.3v v id /2 v cc - (v id /2) v i in input current v cc =0v or 3.6v, v in =0v or 2.8v 20 ma cmos/ lvttl input dc specifications (en, enb, d in1 , d in2 ) v ih input high voltage (lvttl) 2.0 v cc v v il input low voltage (lvttl) gnd 0.8 v i in input current (en, enb, d in1 , d in2 , r inx+ , r inx- ) v in =0v or v cc 20 ma v ik input clamp voltage v ik =-18ma -1.5 -0.7 v lvds output dc specifications (d out1+ , d out1- , d out2+ , d out2- ) v od output differential voltage see figure 4 250 350 450 mv v od v od magnitude change from r l =100 , 35 mv differential low-to-high driver enabled, v os offset voltage see figure 4 1.125 1.250 1.375 v v os offset magnitude change from differential low-to-high 25 mv i os d out+ =0v & d out- =0v, driver enabled -9 ma i osd short-circuit output current v od =0v, driver enabled -9 ma i off power-off input or output current v cc =0v, v out =0v or v cc 20 ma i ozd disabled output leakage current driver disabled, d out+ =0v or v cc or d out- =0v or v cc 10 ma cmos/lvttl output dc specifications (r out1 , r out2 ) v oh output high voltage i oh =-2ma, v id =200mv 2.7 v v ol output low voltage i ol =2ma, v id =200mv 0.25 v i oz disabled output leakage current driver disabled, r outn =0v or v cc 10 ma i cc power supply current (2) drivers enabled, any valid input condition 25 ma i ccz power supply current drivers disabled 10 ma c ind input capacitance lvds input 3.0 pf c out output capacitance lvds output 4.0 pf c int input capacitance lvttl input 3.5 pf note: 2. both driver and receiver inputs are static. all lvds outputs have 100 load. none of the outputs have any lumped capacitive load.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 5 fin1049 ? lvds dual-line driver with dual-line receiver ac electrical characteristics over-supply voltage and operating temperature ranges, unless ot herwise specified. all typical values are at t a =25c and with v cc =3.3v. symbol parameter conditions min. typ. max. units switching characteristics - lvds outputs t plhd differential propagation delay low-to-high see figure 5, figure 6 2 ns t phld differential propagation delay high-to-low 2 ns t tlhd differential output rise time (20% to 80%) 0.2 1.0 ns t thld differential output fall time (80% to 20%) 0.2 1.0 ns t sk(p) pulse skew |t plh - t phl | 0.35 ns t sk(lh), t sk(hl) channel-to-channel skew (3) 0.35 ns t sk(pp) part-to-part skew (4) 1 ns t pzhd differential output enable time, z-to -high see figure 7, figure 8 6 ns t pzld differential output enable time, a-to-low 6 ns t phzd differential output disable time, high-to-z 3 ns t plzd differential output disable time, low-to-z 3 ns f maxd maximum frequency (5) see figure 5 200 mhz switching characteristics - lvttl outputs t phl propagation delay high-to-low measured from 20% to 80% signal 0.5 1.0 3.5 ns t plh propagation delay low-to-high v id =200mv; 0.5 1.0 3.5 ns t sk1 pulse skew distributed load 0 35 400 ps t sk2 channel-to-channel skew c l =15pf and 50 ; 0 50 500 ps t sk3 part-to-part skew r l =1k ; 0 1 ns t lhr transition time low-to-high v os =1.2v; 0.10 0.25 1.40 ns t hlr transition time high-to-low see figure 9, figure 10 0.10 0.18 1.40 ns t phz disable time high-to-z see figure 11, figure 12 2.2 4.5 8.0 ns t plz disable time low-to-z 1.3 3.5 8.0 ns t pzh enable time z-to-high 1.8 3.0 7.0 ns t pzl enable time z-to-low 0.9 1.4 7.0 ns f maxt maximum frequency (6) see figure 9 200 mhz notes: 3. t sk(lh) , t sk(hl) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. 4. t sk(pp) is the magnitude of the difference in propagation del ay times between any specified terminals of two devices switching in the same direction (either low-to-high or high-to-low) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. 5. f maxd generator input conditions: t r =t f < 1ns (10% to 90%), 50% duty cycle, 0v to 3v. output criteria: duty cycle=45% / 55%, v od > 250mv, all channels switch. 6. f maxt generator input conditions: t r =t f < 1ns (10% to 90%), 50% duty cycle, v id =200mv, v cm =1.2v. output criteria: duty cycle=45% / 55%, v oh > 2.7v. v ol < 0.25v, all channels switching.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 6 fin1049 ? lvds dual-line driver with dual-line receiver required specifications and test diagrams notes: 7. electrostatic discharge capability: human body model and machine model esd should be measured using mil-std-883c method 3015.7 standard. 8. latch-up immunity should be tested to t he eia/jedec standard number 78 (eia/jesd78). figure 3. differential receiver voltage definitions test circuit note: 9. c l =15pf, includes all probe and jig capacitances. table 1. receiver minimum and maxi mum input threshold test voltages applied voltages (v) resulting differential input voltage (mv) resulting common mode input voltage (v) v ia v ib v id v ic 1.25 1.15 100 1.2 1.15 1.25 -100 1.2 v cc v cc - 0.1 100 v cc - 0.05 v cc - 0.1 v cc -100 v cc - 0.05 0.1 0.0 100 0.05 0.0 0.1 -100 0.05 1.75 0.65 1100 1.2 0.65 1.75 -1100 1.2 v cc v cc - 1.1 1100 v cc - 0.55 v cc - 1.1 v cc -1100 v cc - 0.55 1.1 0.0 1100 0.55 0.0 1.1 -1100 0.55 figure 4. lvds output circuit for dc test note: 10. r l =100 .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 7 fin1049 ? lvds dual-line driver with dual-line receiver required specifications and test diagrams (continued) figure 5. lvds output propagation dela y and transition time test circuit notes: 11. a: r l =100 . 12. b: z o =50 and c t =15pf distributed. figure 6. lvttl input to lvds output ac waveform
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 8 fin1049 ? lvds dual-line driver with dual-line receiver required specifications and test diagrams (continued) figure 7. lvds output enable / disable delay test circuit notes: 13. a: r l =100 . 14. b: z o =50 and c t =15pf distributed. 15. r1=1000 , r s =950 . 16. v tst =2.4v. figure 8. lvds output enable / disable timing waveforms
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 9 fin1049 ? lvds dual-line driver with dual-line receiver required specifications and test diagrams (continued) figure 9. lvttl output propagation dela y and transition time test circuit notes: 17. a: z o =50 and c t =15pf distributed. 18. r l =100 and r s =950 . figure 10. lvds input to lvttl output propa gation delay and transition time waveforms
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 10 fin1049 ? lvds dual-line driver with dual-line receiver required specifications and test diagrams (continued) figure 11. lvttl output enable / disable test circuit notes: 19. a: z o =50 and c t =15pf distributed. 20. r l =100 , r1=1000 , and r s =950 . figure 12. lvttl output enable / disable timing waveforms
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 11 fin1049 ? lvds dual-line driver with dual-line receiver physical dimensions 0.65 4.40.1 mtc16rev4 0.11 4.55 5.00 5.000.10 12 7.35 4.45 1.45 5.90 figure 13. 16-lead, thin-shrink small-outlin e package (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin1049 ? rev. 1.0.2 12 fin1049 ? lvds dual-line driver with dual-line receiver

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